1. Field of the Invention
This invention relates to improvements in VLSI processor circuits, and more particularly to improvements in methods and apparatus for testing VLSI processor circuits at full speed, with on-chip VLSI circuitry.
2. Description of the Prior Art
As we enter the era of very large scale integration (VLSI), cost and complexity of testing VLSI circuits is becoming significant. The cost of chip failures depends on the levels at which they are detected, the higher the level, the more expensive is the detection and repair. It has been estimated that at each successive level in the hierarchy (chip, board, system, field), the cost of detecting, identifying and replacing faulty chips increases approximately by an order of magnitude. The importance of detecting faulty chips before they reach a board or a system cannot be overemphasized.
A typical single-chip VLSI processor consists of three major blocks, a data path, a control section for controlling the data path, and an on-chip memory. The data path consists of resources to store, manipulate, and transfer data, that is, it contains registers, an arithmetic and logic unit (ALU), and data buses. The current trend in VLSI design is to make the control section microprogrammed, and in such instances a microprogrammed control section is provided which generally consists of on-chip control ROM for storing microinstructions and a sequencer for generating the microinstruction address stream for the control ROM. In addition to the control ROM, on-chip memory on a VLSI processor includes a program ROM for storing machine level programs, and a data RAM for storing data. Examples of such single-chip VLSI processor is manufactured and sold by Texas Instruments Incorporated, Dallas, Tex. are microcomputers TMS 7000 and TMS 99000. Architectures of such prior microcomputers are discussed in articles by J. Hayn et al., "Strip architecture fits microcomputer into less silicon", Electronics, pp. 107-111, Jan. 27, 1981 and by D. Laffitte, "New-generation 16-bit microprocessors-fast and function-oriented", Electronic Design, pp. 111-117, Feb. 19, 1981.
In the semiconductor industry, a test set for the data path of a microprocessor or a microcomputer is typically generated manually, in the form of a machine language program to check its functionality. (The term "functional" is used herein to indicate that the test generation is on only the functional description of the data path to be tested, and not on its low level implementation details, such as logic diagrams and layout information.) The test generation process is very laborious, time consuming, and expensive. In rare circumstances when a test set is graded for its coverage of so called stuck-at faults (usually in response to a demand from major customers), the test designer painfully learns how difficult and expensive it becomes to improve the fault coverage from the initial figure (say a typical 80%) to an ambitious goal (typically over 95%). Though the time required to run a test set for the data path is not usually of paramount importance (the test time is dominated by on-chip memory tests), the large number of manually generated test patterns translates into a large test generation and grading cost, as well as a large amount of test data for a tester.
Though some of these problems are solved by using an automatic test pattern generation (ATPG) system, today's ATGP systems have their own set of problems. Even if an ATPG system is used, the cost of test grading and size of test data volume remains significant. ATPG becomes very expensive as the number of gates and degree of sequentiality (flip-flops) in a circuit increase. It has been suggested that the computer run time for test generation and fault simulation grows as a third power of the number of gates in a circuit. This observation strongly suggests that complex VLSI chips must be designed with the "divide-and-conquer" principle--a fundamental concept for implementing design for testability (DFT) techniques.
Another problem with today's ATPG systems is that they may generate illegal or invalid inputs as test patterns (for example, invalid control signals) that cause the circuit to get into an illegal state. Especially for MOS circuits, an illegal state may cause an unpredictable behavior of a good circuit, or even damage a circuit. Moreover, it may not be possible to generate and apply those invalid test patterns in a built in test (BIT) scenario. Most ATPG systems also require the so-called "equivalent" gate-level description of the circuit. Such a description is usually not available at an early stage of the design cycle when testability evaluation and test pattern generation activities are usually most appropriate. At this early stage what is available is a functional description of the data path. Therefore, at an early stage of design it is difficult to use today's ATPG systems.
Another point that should be brought out is that it is possible to generate a "structural" test set for the data path, using path sensitization techniques (such as the so-called D-algorithm) and its gate-level structural information. However, the test generation process for a structural test set must go through many iterations of test generation and test grading cycles, making it laborious and expensive. In addition to this drawback, the test patterns in a structural test set are unlikely to exhibit any regularity that would make them amenable for built in test (BIT) generation using simple hardware.
The control section of a processor decodes machine instructions and generates control signals for the data path and other logic. As mentioned, the control section of VLSI processors is expected to be microprogrammed rather than implemented with random logic, since a microprogrammed design not only shortens the design cycle time due to its regularity, but also helps improve testability. The test set for the control section is typically written as a machine language program, and testing is done in an indirect fashion by observing the output data produced by the data path. Consequently, the test generation process becomes quite complicated and the size of the test set becomes large, even for checking simple faults in the control section, such as incorrect machine instruction decoding. (See, for example, S. M. Thatte, "VLSI design for testability," IEEE Comput. Soc. Workshop on Fault-tolerant VLSI Design, Santa Monica, Calif. April, 1980, reported in IEEE Computer, Vol. 13, p. 53, Dec., 1980.) If faults causing incorrect sequencing or partial execution of instructions are considered, test generation procedures for generating test sets at the machine program level would become extremely complicated and difficult, if at all possible. Moreover, in a test set for the control section, if the output data produced by the data path is found to be incorrect, it becomes difficult to decide whether to locate the fault in the data path or in the control section, making the diagnosis of errors in prototype chips very difficult. In diagnosis, it is often required to generate control signals which cannot be generated by the control section in normal operation. The difficulties, both in testing as well as diagnosis, are attributed to poor observability as well as controllability of the control section.
Today, tests for on-chip memory on a VLSI processor chip may consume the bulk of the test time for the chip (typically over 80%), because the tests are usually run at the software level, with little hardware or firmware support. A typical ROM test, for instance, may consist of a machine language program to do a cyclic redundancy check on the ROM contents. Typical RAM tests consist of machine language programs implementing RAM testing algorithms, such as the GALPAT, MARCH, WALKING ONES, etc. In addition to large test times, a more serious problem is related to the test quality. Poor test quality stems from the fact that the speed of software-driven test pattern generation does not match the speed of on-chip memory, i.e., the test is not a full speed test. Therefore, such a test may not detect many timing-related problems that show up only at full speed.
It has been suggested to partition a complex circuit into smaller blocks, and use exhaustive combinations of all input patterns as a test set for each block. Examples of such partitioning can be seen in articles by E. J. McCluskey et al., "Design for autonomous test," IEEE Trans. on Comput., vol. C-30, pp. 866-875, Nov, 1981. and S. M. Thatte, "VLSI design for testability," supra.